1. Field of the Invention
The present invention relates to a ferroelectric memory and an operating method therefor, and more particularly, it relates to a ferroelectric memory having a ferroelectric capacitor and an operating method therefor.
2. Description of the Background Art
A ferroelectric memory has recently been watched with interest as a high-speed nonvolatile memory having low power consumption. Therefore, the ferroelectric memory is actively researched and developed.
FIG. 13 is a typical circuit diagram of a most generally employed conventional ferroelectric memory, and FIG. 14 is a sectional view of the ferroelectric memory shown in FIG. 13. Referring to FIGS. 13 and 14, element isolation regions 102 are formed on prescribed regions of the surface of a semiconductor substrate 101 in the structure of the conventional ferroelectric memory. Source regions 103 and a drain region 104 are formed on an element forming region enclosed with the element isolation regions 102 at prescribed intervals. Gate electrodes 106 forming word lines WL0 and WL1 are provided on channel regions located between the source regions 103 and the drain region 104. A bit line BL0 is electrically connected to the drain region 104.
Lower electrodes 109 are formed on the source regions 103 through plug electrodes 108. Upper electrodes 111 forming plate lines PL0 and PL1 are formed on the lower electrodes 109 through ferroelectric layers 110. The lower electrodes 109, the ferroelectric layers 110 and the upper electrodes 111 form ferroelectric capacitors 112. The source regions 103, the drain region 104 and the gate electrodes 106 form transistors 107. The transistors 107 function as switches for selecting memory cells 100. As shown in FIG. 13, each memory cell 100 is formed by a single transistor 107 and a single ferroelectric capacitor 112.
In the structure of the conventional ferroelectric memory shown in FIGS. 13 and 14, however, each memory cell 100 formed by the single transistor 107 and the single ferroelectric capacitor 112 disadvantageously requires a relatively large area.
In this regard, there has generally been developed a simple matrix ferroelectric memory having memory cells each formed by only a single ferroelectric capacitor or an MFIS-FET (metal ferroelectric insulator semiconductor-field effect transistor) or MFMIS-FET (metal ferroelectric metal insulator semiconductor-field effect transistor) ferroelectric memory having ferroelectric capacitors formed on gate portions of transistors.
FIG. 15 is a circuit diagram of a conventional simple matrix ferroelectric memory, and FIG. 16 is a sectional view of the simple matrix ferroelectric memory shown in FIG. 15. Referring to FIGS. 15 and 16, a ferroelectric layer 202 is formed on each bit line (BL) 201. Word lines (WL) 203 are formed on the ferroelectric layer 202 in a direction intersecting with the bit line 201. The bit line 201, the ferroelectric layer 202 and each word line 203 form a ferroelectric capacitor 210. In this simple matrix ferroelectric memory, each memory cell 200 is formed by only a single ferroelectric capacitor 210, as shown in FIG. 15.
FIG. 17 is a circuit diagram for illustrating exemplary voltage application according to a ½ Vcc method in a write operation of the conventional simple matrix ferroelectric memory, and FIG. 18 is a circuit diagram for illustrating exemplary voltage application according to a ⅓ Vcc method in the write operation of the conventional simple matrix ferroelectric memory.
Referring to FIG. 17, a power supply voltage Vcc is applied between a bit line BL1 and a word line WL1 connected with a selected memory cell (selected cell) for driving the selected cell according to the ½ Vcc method. In other words, the power supply voltage Vcc is applied to the bit line BL1 while a voltage of 0 V is applied to the word line WL1. Further, a voltage of 0 V is applied to bit lines BL0 and BL2 connected with non-selected memory cells (non-selected cells) and a voltage of ½ Vcc is applied to word lines WL0 and WL2 connected with the non-selected cells. Thus, the power supply voltage Vcc is applied to the selected cell while the voltage of ½ Vcc is applied to the non-selected cells.
Referring to FIG. 18, the power supply voltage Vcc is applied to the bit line BL1 while a voltage of 0 V is applied to the word line WL1 according to the ⅓ Vcc method. Further, a voltage of ⅓ Vcc is applied to the bit lines BL0 and BL2 connected with the non-selected memory cells (non-selected cells) and a voltage of ⅔ Vcc is applied to the word lines WL0 and WL2 connected with the non-selected cells. Thus, the power supply voltage Vcc is applied to the selected cell while the voltage of ⅓ Vcc is applied to the non-selected cells.
In the aforementioned case, it is necessary that polarization inversion can be sufficiently saturated with respect to the ferroelectric layer 202 (see FIG. 16) of the selected cell while polarized states remain substantially unchanged with respect to ferroelectric layers of the non-selected cells.
Under present conditions, however, the angular shape of a ferroelectric hysteresis is so insufficient that information (quantity of charges) is lost by the so-called disturbance when the voltage of ½ Vcc or ⅓ Vcc is unidirectionally continuously applied to the non-selected cells, as shown in FIG. 19. Information written in the non-selected cells is lost due to such disturbance, and hence it is difficult to use the memory as a ferroelectric memory in this case. At present, therefore, it is regarded as difficult to put the simple matrix ferroelectric memory shown in FIGS. 15 and 16 into practice.
FIG. 20 is a circuit diagram showing a conventional one-transistor ferroelectric memory having memory cells formed by MFMIS-FETs, and FIG. 21 is a sectional view showing the one-transistor ferroelectric memory shown in FIG. 20. Referring to FIGS. 20 and 21, a well region 302 is formed on the surface of a semiconductor substrate 301 in the one-transistor ferroelectric memory. Source regions 303 and a drain region 304 are formed on the surface of the well region 302 at prescribed intervals. Gate electrodes 306 are formed on channel regions located between the source regions 303 and the drain region 304 through gate insulator films 305.
Word lines (WL0 and WL1) 308 are formed on the gate electrodes 306 through ferroelectric layers 307. A bit line (BL0) 310 is electrically connected to the drain region 304. Plate lines (PL0 and PL1) 311 are connected to the source regions 303. A source line (SL) 312 is connected to the well region 302. The gate electrodes 306, the ferroelectric layers 307 and the word lines 308 form ferroelectric capacitors 315. The source regions 303, the drain region 304, the gate insulator films 305 and the gate electrodes 306 form transistors 309. In this case, each memory cell 300 has a structure obtained by forming each ferroelectric capacitor 315 on a gate portion of each transistor 309.
FIG. 22 is an equivalent circuit diagram of the one-transistor ferroelectric memory shown in FIGS. 20 and 21 in writing. When writing is performed similarly to that in the simple matrix ferroelectric memory shown in FIGS. 17 and 18 by unidirectionally continuously applying a voltage of ½ Vcc or ⅓ Vcc to non-selected cells, therefore, information (quantity of charges) is disadvantageously lost by the so-called disturbance.